邏輯設(shè)計基礎(chǔ)

前言

This book is intended as an introductory logic design book for  students in computer science, computer engineering, and electrical engineering. It has no prerequisites, although the maturity  attained through an introduction to engineering course or a first programming course would be helpful.  The book stresses fundamentals. It teaches through a large number  of examples. The philosophy of the author is that the only way to learn  logic design is to do a large number of design problems. Thus, in addition to the numerous examples in the body of the text, each chapter has a  set of Solved Problems, that is, problems and their solutions, a large set  of Exercises (with answers to selected exercises in Appendix B), and a  Chapter Test (with answers in Appendix C). In addition, there are a set of  laboratory experiments that tie the theory to the real world. Appendix A  provides the background to do these experiments with a standard hardware laboratory (chips, switches, lights, and wires), a breadboard simulator (for the PC or Macintosh), and two schematic capture tools. The  course can be taught without the laboratory, but the student will benefit  significantly from the addition of 8 to 10 selected experiments.  Although computer-aided tools are widely used for the design of  large systems, the student must first understand the basics. The basics  provide more than enough material for a first course. The schematic capture laboratory exercises and a section on Hardware Design Languages  in Chapter 8 provide some material for a transition to a second course  based on one of the computer-aided tool sets.  Chapter 1 gives a brief overview of number systems as it applies to  the material of this book. (Those students who have studied this in an  earlier course can skip to Section 1.2.) It then discusses the steps in the  design process for combinational systems and the development of truth  tables.  Chapter 2 introduces switching algebra and the implementation of  switching functions using common gates-AND, OR, NOT, NAND,  NOR, Exclusive-OR, and Exclusive-NOR. We are only concerned with  the logic behavior of the gates, not the electronic implementation.  Chapter 3 deals with simplification using the Karnaugh map. It provides methods for solving problems (up to six variables) with both single  and multiple outputs.  Chapter 4 introduces two algorithmic methods for solving combinational problems-the Quine-McCluskey method and Iterated Consensus. Both provide all of the prime implicants of a function or set of   ix   x Preface   functions, and then use the same tabular method to find minimum sum of  products solutions.  Chapter 5 is concerned with the design of larger combinational  systems. It introduces a number of commercially available larger devices, including adders, comparators, decoders, encoders and priority  encoders, and multiplexers. That is followed by a discussion of the use  of logic arrays-ROMs, PLAs, and PALs for the implementation of  medium scale combinational systems. Finally, two larger systems are  designed.  Chapter 6 introduces sequential systems. It starts by examining the  behavior of latches and flip flops. It then discusses techniques to analyze  the behavior of sequential systems.  Chapter 7 introduces the design process for sequential systems. The  special case of counters is studied next. Finally, the solution of word  problems, developing the state table or state diagram from a verbal  description of the problem is presented in detail.  Chapter 8 looks at larger sequential systems. It starts by examining  the design of shift registers and counters. Then, PLDs are presented.  Three techniques that are useful in the design of more complex  systems-ASM diagrams, one-shot encoding, and HDLs-are discussed  next. Finally, two examples of larger systems are presented.  Chapter 9 deals with state reduction and state assignment issues.  First, a tabular approach for state reduction is presented. Then partitions  are utilized both for state reduction and for achieving a state assignment  that will utilize less combinational logic.  A feature of this text is the Solved Problems. Each chapter has a  large number of problems, illustrating the techniques developed in the  body of the text, followed by a detailed solution of each problem. Students are urged to solve each problem (without looking at the solution)  and then compare their solution with the one shown.  Each chapter contains a large set of exercises. Answers to a selection  of these are contained in Appendix B. Solutions will be made available  to instructors through the Web. In addition, each chapter concludes with  a Chapter Test; answers are given in Appendix C.  Another unique feature of the book is the laboratory exercises, included in Appendix A. Four platforms are presented-a hardware based  Logic Lab (using chips, wires, etc.); a hardware lab simulator that allows  the student to “connect” wires on the computer screen; and two circuit  capture programs, LogicWorks 4 and Altera Max+plus II. Enough  information is provided about each to allow the student to perform a  variety of experiments. A set of 26 laboratory exercises are presented.  Several of these have options, to allow the instructor to change the  details from one term to the next.  We teach this material as a four-credit course that includes an  average of 31/2 hours per week of lecture, plus, typically, eight laboratory exercises. (The lab is unscheduled; it is manned by Graduate   Preface xi   Assistants 40 hours per week; they grade the labs.) In that course we  cover  Chapter 1: all of it  Chapter 2: all but 2.11  Chapter 3: all of it  Chapter 4: if time permits at the end of the semester  Chapter 5: all but 5.8. However, there is a graded design problem  based on that material (10 percent of the grade; students usually  working in groups of 2 or 3).  Chapter 6: all of it  Chapter 7: all of it  Chapter 8: 8.1, 8.2, 8.3. We sometimes have a second project based  on 8.7.  Chapter 9 and Chapter 4: We often have some time to look at one  of these. We have never been able to cover both.  With less time, the coverage of Section 2.10 could be minimized.  Section 3.5 is not needed for continuity; Section 3.6 is used somewhat in  the discussion of PLAs in Section 5.7.2. Chapter 5 is not needed for anything else in the text, although many of the topics are useful to students  elsewhere. The instructor can pick and choose among the topics. The SR  and T flip flops could be omitted in Chapters 6 and 7. Sections 7.2 and 7.3  could be omitted without loss of continuity. As is the case for Chapter 5,  the instructor can pick and choose among the topics of Chapter 8. With a  limited amount of time, Section 9.1 could be covered. With more time, it  could be skipped and state reduction taught using partitions (9.2 and 9.3).  ACKNOWLEDGMENTS  I want to thank my wife, Allyn, for her encouragement and for enduring  endless hours when I was closeted in my office working on the manuscript. Several of my colleagues at Florida Atlantic University have read  parts of the manuscript and have taught from earlier drafts. I wish to acknowledge especially Mohammad Ilyas, Imad Mahgoub, Oge Marques,  Imad Jawhar, Abhi Pandya, and Shi Zhong for their help. In addition, I  wish to express my appreciation to my chairs, Mohammad Ilyas, Roy  Levow, and Borko Fuhrt who made assignments that allowed me to work  on the book. Even more importantly, I want to thank my students who  provided me with the impetus to write a more suitable text, who suffered  through earlier drafts of the book, and who made many suggestions and  corrections. I want to thank Visram Rathnam for his contributions to the  section on Altera tools. The reviewers-  Michael McCool, University of Waterloo;  Pinaki Mazumder, University of Michigan;   xii Preface  Nick Phillips, Southern Illinois University;  Gary J. Minden, University of Kansas;  Daniel J. Tylavsky, Arizona State University;  Nadar I. Rafla, Boise State University;  Dan Stanzione, Clemson University;  Frank M. Candocia, Florida International University;  Lynn Stauffer, Sonoma State University;  Rajeev Barua, University of Maryland-  provided many useful comments and suggestions. The book is much  better because of their efforts. Finally, the staff at McGraw-Hill, particularly Carlise Paulson, Melinda Dougharty, Jane Mohr, Betsy Jones,  Barbara Somogyi, Rick Noel, Sandy Ludovissy, Audrey Reiter, and Dawn  Bercier have been indispensable in producing the final product, as has  Michael Bohrer-Clancy at Interactive Composition Corporation.

內(nèi)容概要

邏輯設(shè)計是計算機科學(xué)、計算機工程和電氣工程等專業(yè)的理論基礎(chǔ)。學(xué)好邏輯設(shè)計需要三個環(huán)節(jié)：理論知識、習(xí)題和實驗。因此，本書在強調(diào)基礎(chǔ)知識的同時，結(jié)合著大量實例進行講授，并給出了大量例題，同時還附有大量習(xí)題和每章的測驗題。此外，還安排有4個實驗操作平臺和26個實驗，以便把理論和實踐緊密聯(lián)系起來。    本書是計算機、電氣工程和通信、電子等專業(yè)的學(xué)生學(xué)習(xí)邏輯設(shè)計的教材，同時也是相關(guān)專業(yè)工程技術(shù)人員的參考用書。

作者簡介

作者：(美國)馬科維茲 (Marcovitz.A.B.)

書籍目錄

Preface Chapter Introduction  1.1 A Brief Review of Number Systems    1.2 The Design Process for Combinational Systems  1.3 Don’t Care Conditions  1.4 The Development of Truth Tables    1.5 The Laboratory   1.6 Solved Problems    1.7 Exercises   1.8 Chapter 1 Test  Chapter 2 Switching Algebra and Logic Circuits 　2.1 Definition of Switching Algebra　2.2 Basic Properties of Switching Algebra  　2.3 Manipulation of Algebraic Functions 　2.4 Implementation of Functions with AND, OR, and NOT Gates 　2.5 From the Truth Table to Algebraic Expressions  　2.6 Introduction to the Karnaugh Map 　2.7 The Complement and Product of Sums  　2.8 NAND, NOR, and Exclusive-OR Gates  　2.9 Simplification of Algebraic Expressions  　2.10 Manipulation of Algebraic Functions and NAND Gate Implementations 　2.11 A More General Boolean Algebra　2.12 Solved Problems 　2.13 Exercises 　2.14 Chapter 2 Test Chapter 3 The Karnaugh Map  　3.1 Minimum Sum of Product Expressions Using the Karnaugh Map 　3.2 Don’t Cares　3.3 Product of Sums 　3.4 Minimum Cost Gate Implementations 　3.5 Five- and Six-Variable Maps 　3.6 Multiple Output Problems　3.7 Solved Problems 　3.8 Exercises  　3.9 Chapter 3 Test  Chapter 4 Function Minimization Algorithms 　4.1 Quine-McCluskey Method for One Output 　4.2 Iterated Consensus for One Output　4.3 Prime Implicant Tables for One Output  　4.4 Quine-McCluskey for Multiple Output Problems 　4.5 Iterated Consensus for Multiple Output Problems  　4.6 Prime Implicant Tables for Multiple Output Problems 　4.7 Solved Problems 　4.8 Exercises  　4.9 Chapter 4 Test Chapter 5 Larger Combinational Systems　5.1 Delay in Combinational Logic Circuits  　5.2 Adders and Other Arithmetic Circuits 　5.3 Decoders　5.4 Encoders and Priority Encoders  　5.5 Multiplexers　5.6 Three-State Gates  　5.7 Gate Arrays—ROMs, PLAs, and PALs　5.8 Larger Examples  　5.9 Solved Problems 　5.10 Exercises  　5.11 Chapter 5 Test Chapter 6 Analysis of Sequential Systems　6.1 State Tables and Diagrams 　6.2 Latches and Flip Flops 　6.3 Analysis of Sequential Systems　6.4 Solved Problems 　6.5 Exercises 　6.6 Chapter 6 Test  Chapter 7 The Design of Sequential Systems 　7.1 Flip Flop Design Techniques　7.2 The Design of Synchronous Counters 　7.3 Design of Asynchronous Counters 　7.4 Derivation of State Tables and State Diagrams 　7.5 Solved Problems　7.6 Exercises 　7.7 Chapter 7 Test Chapter 8 Solving Larger Sequential Problems 　8.1 Shift Registers 　8.2 Counters　8.3 Programmable Logic Devices (PLDs) 　8.4 Design Using ASM Diagrams 　8.5 One-Shot Encoding 　8.6 Hardware Design Languages 　8.7 More Complex Examples 　8.8 Solved Problems 　8.9 Exercises 　8.10 Chapter 8 Test  Chapter 9 Simplification of Sequential Circuits　9.1 ATabular Method for State Reduction 　9.2 Partitions  　9.3 State Reduction Using Partitions 　9.4 Choosing a State Assignment 　9.5 Solved Problems 　9.6 Exercises 　9.7 Chapter 9 Test Appendix A Laboratory Experiments　A.1 Hardware Logic Lab  　A.2 WinBreadboard. and MacBreadboard　A.3 Introduction to LogicWorks 4 　A.4 Introduction to Altera Max+plusII　A.5 A Set of Logic Design Experiments  Appendix B Answers to Selected Exercises Appendix C Chapter Test Answers Index

章節(jié)摘錄

插圖：

圖書封面

圖書標(biāo)簽Tags

無

評論、評分、閱讀與下載

---

    邏輯設(shè)計基礎(chǔ) PDF格式下載

---