System Verilog數(shù)字系統(tǒng)設(shè)計(jì)

內(nèi)容概要

　　SystemVerilog是21世紀(jì)電子設(shè)計(jì)師必須掌握的最重要的語(yǔ)言之一，因?yàn)樗窃O(shè)計(jì)和驗(yàn)證復(fù)雜電子系統(tǒng)核心芯片的重要手段。由馬克編寫的這本《System
Verilog
數(shù)字系統(tǒng)設(shè)計(jì)(影印版)》是用SystemVerilog語(yǔ)言設(shè)計(jì)并驗(yàn)證數(shù)字系統(tǒng)的基本概念和具體方法。在介紹基本語(yǔ)法的基礎(chǔ)上，闡述了如何用
SystemVerilog構(gòu)成數(shù)字電路、組件和系統(tǒng)，以及應(yīng)該如何使用SystemVerilog搭建測(cè)試平臺(tái)，并對(duì)設(shè)計(jì)進(jìn)行驗(yàn)證。
《System Verilog數(shù)字系統(tǒng)設(shè)計(jì)(影印版)》既適合作電子、自動(dòng)化和計(jì)算機(jī)專業(yè)本科生和研究生的教科書，也適合已經(jīng)掌握
Verilog和VHDL硬件描述語(yǔ)言的工程師使用。

書籍目錄

List of Figures
List of Tables
Preface
Acknowledgments
About the Author
1.Introduction
2.Combinational Logic Design
3.Combinational Logic Using SystemVerilog Gate Models
4.Combinational Building Blocks
5.SystemVerilog Models of Sequential Logic Blocks
6.Synchronous Sequential Design
7.Complex Sequential Systems
8.Writing Testbenches
9.SystemVerilog Simulation
10.SystemVerilog Synthesis
11.Testing Digital Systems
12.Design for Testability
13.Asynchronous Sequential Design
14.Interfacing with the Analog World
A.SystemVerilog and Verilog
Awe to Selected Exercises
Bibliography
Index

章節(jié)摘錄

版權(quán)頁(yè)：   插圖：   3.5 Logic Values In the preceding description,we mentioned logic values and referred briefly to a high impedance state.SystemVerilog allows wires to take four possible values: 0,1,x (unknown),and z (high impedance).In general,logic gates are designed to generate 0 or 1 at the outputs,x usually indicates some kind of anomalous situation-perhaps an unimtialized flip-flop or a wire that is being driven to two different values by two gates simultaneously. The high-impedance state,z,is used to model the output of three-state buffers.The purpose of three-state buffers is to allow the outputs of gates to be connected together to form buses,for example.The x state is normally generated when different outputs from two gates are connected together.We would expect,however,that a 1 and a z (or a 0 and a z) driving the same wire would resolve to a 1 (or a 0).Clearly,therefore,not all logic values are equal. The unknown and high-impedance states can be written as lower case ("x" and "z") or upper case ("X" and "Z") characters.The question mark ("?") can be used as an alternative to the high-impedance state. 3.6 Continuous Assignments The two-input AND gate at the beginning of the chapter was written using a continuous assignment.In general,continuous assignments are used to assign values to nets.In later chapters,we will see that alwaya comb and always ff procedural blocks are more useful for describing synthesizable hardware.Continuous assignments are,on the other hand,the most convenient way to describe three-state buffers and to model delays in combinational logic.Three-state buffers will be discussed in more detail in the next chapter.This is an appropriate point,however,to discuss SystemVerilog operators.

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《國(guó)外電子信息精品著作:System Verilog數(shù)字系統(tǒng)設(shè)計(jì)(影印版)》既適合作電子、自動(dòng)化和計(jì)算機(jī)專業(yè)本科生和研究生的教科書，也適合已經(jīng)掌握Verilog和VHDL硬件描述語(yǔ)言的工程師使用。

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